Method of forming bipolar transistor having substrate to polysilicon extrinsic base contact

Patent 5204277 Issued on April 20, 1993. Estimated Expiration Date:

February 3, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method of manufacturing bipolar transistor
Patent #: 4980305
Issued on: 12/25/1990
Inventor: Kadota, et al.

Method of manufacturing semiconductor device Patent #: 5028550
Issued on: 07/02/1991
Inventor: Hirakawa

Inventors

Assignee

Motorola, Inc.

Application

No. 829669 filed on 02/03/1992

US Classes:

438/366, Having sidewall257/E21.375, Silicon vertical transistor (EPO)257/E21.507Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)

Examiners

Primary: Chaudhuri, Olik
Assistant: Pham, Long

Attorney, Agent or Firm

King; Robert L.

Foreign Patent References

0329401 EP 08/13/1989
0375323 EP 06/13/1990
0246874 JP 10/13/1989
0246338 JP 10/13/1990
2243488 GB 10/13/1991

International Classes

H01L 021/265
H01L 029/70

Abstract

A bipolar transistor (10) with reduced substrate trenching and reduced base electrode size. A substrate (12) is provided with an overlying first dielectric layer (20), an overlying first conductive layer (24), an overlying second dielectric layer (26), and a doped collector region (14, 16, and 18). An opening is formed within the layers (20, 24, and 26) forming a sidewall of conductive layer (24). A doped base diffusion (28) is formed within a portion of the substrate (12) exposed by the opening. A conductive grown region (30) is formed laterally adjacent the sidewall of conductive layer (24) and overlies substrate (12). A spacer (32) is formed adjacent a first portion of the conductive grown region (30). A second portion of the conductive grown region (30) is removed forming an exposed portion of substrate (12). A second spacer (36) is formed adjacent spacer (32). A conductive layer (38), which forms a doped emitter region is formed overlying the exposed portion of substrate (12).

Other References

Innovations in Silicon Deposition Technology for Advanced Device Structures, by David L. Haram et al., was partially published in Electron Device Letters, vol. 9, May 1988, pp. 259-261
Selective Epitaxial Growth of Silicon and Some Potential Applications, by B. J. Ginsberg et al., was published in IBM Journal of Research and Development, vol. 34, No. 6, Nov. 1990, pp. 816-827
A Novel Self-Aligned Epitaxial Base Transistor, by H. Fujimaki et al., was published and present via IEEE 1991 Bipolar Circuits and Technology Meeting 3.2, pp. 59-62 (date unknown