Method for making a shallow junction bipolar transistor and transistor formed thereby
April 3, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3604986 3775192 Self-aligned bipolar transistor with inverted polycide base contact Process of fabricating MOS devices having shallow source and drain junctions Method for forming self-aligned emitters and bases and source/drains in an integrated circuit Process for formation of shallow silicided junctions Bicmos process for forming shallow npn emitters and mosfet source/drains High speed double polycide bipolar/CMOS integrated circuit process Patent #: 4902640 InventorAssigneeApplicationNo. 679896 filed on 04/03/1991US Classes:438/330, Resistor257/E21.375, Silicon vertical transistor (EPO)257/E29.185, Having emitter-base junction and base-collector junction on different surfaces (e.g., mesa planar transistor) (EPO)438/366, Having sidewall438/370Forming buried region (e.g., implanting through insulating layer, etc.)ExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmInternational ClassH01L 021/265AbstractDisclosed is a process for forming a bipolar transistor at the face (22) of a semiconductor layer. A refractory metal layer (34) is deposited on the face (22) to cover a base area (38) thereof. A dopant (40) is implanted through the metal layer (34) within the base area (38) to penetrate the face (22). The metal layer (34) is then removed from the face within an emitter area (48) contained within the base area (38). A dopant is then diffused into the face within the emitter area (48). Finally, the dopants are annealed to form a shallow base region (66) that spaces an emitter region (64) from a collector region (12, 14). The process of the invention can form a high-concentration emitter/base junction only 400 Angstroms from the surface of the semiconductor layer. | |
