Method of fabricating silicon-based carriers
August 20, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3288639 3878554 Opto-isolators and method of manufacture Low stress semiconductor device lead connection Method of fabricating complex micro-circuit boards and substrates Forming interconnections for multilevel interconnection metallurgy systems Process of making multi-layer ceramic package Pre-alloyed thick film conductor for use with aluminum wire bonding and method of bonding Providing circuit lines on a substrate Methods for developing high speed chip carriers with impedance matching packaging InventorsAssigneeApplicationNo. 747523 filed on 08/20/1991US Classes:438/384, Deposited thin film resistor257/E23.008, Semiconductor insulating substrates (EPO)438/107, Assembly of plural semiconductive substrates each possessing electrical device438/396, Stacked capacitor438/612, Forming solder contact or bonding pad438/622, Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)438/627At least one layer forms a diffusion barrierExaminersPrimary: Hearn, Brian E.Assistant: Trinh, Michael Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/302AbstractSilicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.Other References
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