Method for manufacturing BICMOS devices
April 27, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesI2 L Structure and fabrication process compatible with high voltage bipolar transistors Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors Method of fabricating an integrated circuit containing bipolar and MOS transistors Method for manufacturing a Bi-CMOS device Process for fabricating an integrated circuit Method for making bipolar/CMOS IC with isolated vertical PNP Method of making a complementary BiCMOS process with isolated vertical PNP transistors Bi-CMOS integrated circuit device having a high speed lateral bipolar transistor Process for fabricating high performance BiCMOS circuits Patent #: 5079177 InventorsAssigneeApplicationNo. 874612 filed on 04/27/1992US Classes:438/203, Complementary bipolar transistors257/E21.696, Bipolar and MOS technologies (EPO)438/207Including isolation structureExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmInternational ClassH01L 021/265Foreign Application Priority Data1991-11-14 KRAbstractA method for BICMOS devices is disclosed, wherein an emitter and a base of a vertical PNP transistor are self-aligned, an extrinsic base is formed by adapting a base electrode polysilicon layer as a diffusion source, and the base electrode and an intrinsic base are coupled by diffusion of N type impurities adapting the N+ polysilicon as a diffusion source, so that the manufacturing process is simplified and the resistance of the extrinsic base is reduced. | |
