BICMOS device and manufacturing method thereof
Patent 5192992 Issued on March 9, 1993. Estimated Expiration Date: 
November 18, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 18, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor device High voltage bipolar transistor in BiCMOS Patent #: 5102811 InventorsAssigneeApplicationNo. 794739 filed on 11/18/1991US Classes:257/370, Combined with bipolar transistor257/377, With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)257/413, Polysilicon laminated with silicide257/554, With connecting region made of polycrystalline semiconductor material (e.g., polysilicon base contact)257/E21.2, Conductor comprising metal or metallic silicide formed by deposition e.g., sputter deposition, i.e., without silicidation reaction (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E27.015, In combination with bipolar transistor (EPO)438/203Complementary bipolar transistorsExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmInternational ClassesH01L 027/02H01L 021/265 Foreign Application Priority Data1991-06-27 KRAbstractA BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors. | |
