Method of manufacturing SOI semiconductor element
Patent 5188973 Issued on February 23, 1993. Estimated Expiration Date: 
April 30, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 30, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated circuit manufacturing method Method for making planar FET having gate, source and drain in the same plane Manufacturing method for semiconductor device Patent #: 5120666 InventorsAssigneeApplicationNo. 877446 filed on 04/30/1992US Classes:438/157, Plural gate electrodes (e.g., dual gate, etc.)257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E29.275, With multiple gates (EPO)257/E29.286, Monocrystalline only (EPO)438/589Recessed into semiconductor substrateExaminersPrimary: Thomas, TomAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/70Foreign Application Priority Data1991-05-09 JPAbstractAccording to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.Other References
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