Method of manufacturing field-effect transistors designed for operation at very high frequencies, using integrated techniques
Methods of defining regions of crystalline material of the group III-V compounds
Dry etching of copper patterns
Method of manufacturing field-effect transistors with self-aligned grid and transistors thus obtained
Method for the selective dry etching of layers of III-V group semiconductive materials
Method of fabricating semiconductor devices
Plasma etching using a bilayer mask
Method of wet etching by use of carbonaceous masks Patent #: 5102498
ApplicationNo. 866716 filed on 04/10/1992
US Classes:438/606, Ga and As containing semiconductor216/40, FORMING PATTERN USING LIFT OFF TECHNIQUE216/66, Using ion beam, ultraviolet, or visible light216/81, Etching elemental carbon containing substrate257/E21.222, Vapor phase etching (EPO)257/E21.232, Characterized by their composition, e.g., multilayer masks, materials (EPO)438/656, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/670, Utilizing lift-off438/671, Utilizing multilayered mask438/686, Noble group metal (i.e., silver (Ag), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), or alloy thereof)438/930, TERNARY OR QUATERNARY SEMICONDUCTOR COMPRISED OF ELEMENTS FROM THREE DIFFERENT GROUPS (E.G., I-III-V, ETC.)438/945, Special (e.g., metal, etc.)438/951Lift-off
ExaminersPrimary: Quach, T. N.
Attorney, Agent or Firm
Foreign Patent References
International ClassesH01L 021/283
AbstractA method is described for forming patterns in deposited overlayers on GaAs and for aligning the formed patterns with etch features produced through dry processing. The deposited overlayers on GaAs are protected during pattern formation and subsequent processing by a durable, process integrable mask of hydrogenated amorphous carbon.