U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Interconnecting network

Patent 5175539 Issued on December 29, 1992. Estimated Expiration Date: Icon_subject November 21, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3546390

3674938

3842214

3928730

Three stage minimum configuration conditionally non-blocking matrix
Patent #: 4394541
Issued on: 07/19/1983
Inventor: Seiden

Electronically controlled interconnection system
Patent #: 4539564
Issued on: 09/03/1985
Inventor: Smithson

Broadcast packet switching network
Patent #: 4734907
Issued on: 03/29/1988
Inventor: Turner

Non-blocking optical space switch Patent #: 4837855
Issued on: 06/06/1989
Inventor: Hajikano ,   et al.

Inventor

Assignee

Application

No. 617914 filed on 11/21/1990

US Classes:

340/2.21, Plural stages370/388, Multistage switch379/272Path selection or routing

Examiners

Primary: Yusko, Donald J.
Assistant: Weissman, Peter S.

Attorney, Agent or Firm

International Class

H04J 003/00

Foreign Application Priority Data

1989-01-24 DE

Abstract

Interconnecting network for simultaneous selective connecting of each of N inputs to one of N outputs has an input section which includes the inputs and contains at least the consecutive stages 1 to n-1 of a n-stage baseline network and has N outputs, and an output section which has N inputs which are connected to the N outputs of the input section, includes a n-stage baseline network and has N outputs which form the outputs of the interconnecting network. The order of the n-1 stages following the inputs is the same in both baseline networks.

Other References

  • "Computer Architecture and Parallel Processing", K. Hwang and F. A. Briggs, cGraw Hill Intl. Editions, Computer Science Series (1984); pp. 332, 333 and 338
  • "On the Rearrangeability of 2(log2 N)-1 Stage Permutation Networks", Kyungsook Yoon Lee, IEEE Transactions on Computers, vol. C-34, No. 5, May, 1985, pp. 412-425
  • "Parallel Processing and Interconnection Networks", Chuan-lin Wu, Department of Electrical and Computing Engineering, The University of Texas at Austin, Aug. 20, 1985, pp. 50-5
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