Method of producing insulated-gate field effect transistor
March 18, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for fabricating lightly doped drain MOS devices CMOS integrated circuit with reduced susceptibility to PMOS punchthrough Method for fabricating double implanted LDD transistor self-aligned with gate LDD transistor process having doping sensitive endpoint etching MOS transistors using selective polysilicon deposition Bipolar process using selective silicon deposition Method of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions Method of fabricating MOS transistors using selective polysilicon deposition Patent #: 5082794 InventorAssigneeApplicationNo. 670806 filed on 03/18/1991US Classes:438/290, After formation of source or drain regions and gate electrode257/E21.205, Characterized by sectional shape, e.g., T-shape, inverted T, spacer (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E29.269, With overlap between lightly doped extension and gate electrode (EPO)438/291, Using channel conductivity dopant of opposite type as that of source and drain438/305, Plural doping steps438/919Compensation dopingExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/265Foreign Application Priority Data1990-03-19 JPAbstractA polysilicon layer of approximately 500Å in thickness and a PSG layer approximately 3000Å in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming a side wall layer made of PSG of predetermined thickness in the opening, a second polysilicon layer for a leg portion of an inverse-T gate is embedded in the opening and both PSG layers are removed. Then, n- impurities are doped by ion implantation by using the second polysilicon layer as a mask, forming a LDD region. Another side wall layer is formed on the second polysilicon layer, and then, the first polysilicon layer, exposed outside of the second polysilicon layer and the side wall layer, is etched. Under the side wall layer, that polysilicon layer constituting a top of the inverse-T gate remains. Ion implantation is implemented by using the second polysilicon layer and the side wall layer as masks, such that a n+ source and n+ drain are formed. Since the n- impurities are doped by the ion implantation through the first polysilicon layer having an even thickness, the junction depth in the LDD region is constant. Additionally, since the thickness of the first polysilicon layer is small, the gate insulating layer reliably functions as an etch-stop in patterning the polysilicon layer. | |
