Digital phase lock clock generator without local oscillator
December 22, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3436647 3883810 Programmable variable length high speed digital delay line Phase synchronizer Gain imbalance corrected quadrature phase detector Self-calibrated clock and timing signal generator for MOS/VLSI circuitry Controlled phase off-set digital test system Digital phase locked loop CMOS integrated circuit for signal delay Digital phase lock loop InventorsAssigneeApplicationNo. 391689 filed on 08/10/1989US Classes:327/158, With variable delay means327/159, With digital element327/160, With counter327/238, Quadrature related (i.e., 90 degrees)327/250, With active time delay element327/295, Plural outputs375/374With charge pump or up and down countersExaminersPrimary: Callahan, Timothy P.Attorney, Agent or FirmInternational ClassesH03K 005/13H03K 005/22 AbstractA digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.Other References
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