Method for forming a thick base oxide in a BiCMOS process
October 29, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated circuit manufacturing method Method of making a monolithic integrated circuit comprising at least one pair of complementary field-effect transistors and at least one bipolar transistor Process for manufacturing a monolithic integrated solid-state circuit having at least one insulated-gate field-effect transistor and at least one bipolar transistor Method of forming bifets by forming isolation regions connected by diffusion in semiconductor substrate and epitaxial layer Semiconductor device and manufacturing method thereof MOS-cascoded bipolar current sources in non-epitaxial structure Method of making a planar structure containing MOS and bipolar transistors Protection device in an integrated circuit Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate InventorsAssigneeApplicationNo. 785174 filed on 10/29/1991US Classes:438/207, Including isolation structure257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.375, Silicon vertical transistor (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E27.015, In combination with bipolar transistor (EPO)438/231, Plural doping steps438/234, Including bipolar transistor (i.e., BiMOS)438/303Utilizing gate sidewall structureExaminersPrimary: Chaudhuri, OlikAssistant: Fourson, G. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/72AbstractA BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors. Subsequent patterning and etching of the polysilicon, followed by sidewall filament formation and source/drain doping, is performed to complete the structure.Other References
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