Method of fabricating an high-performance insulated-gate field-effect transistor
October 12, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFabrication technique for integrated circuits Method in the manufacture of integrated circuits Process for manufacturing semiconductor BICMOS device Double implanted LDD transistor self-aligned with gate Method of making cmos with shallow source and drain junctions LDD transistor process having doping sensitive endpoint etching Bipolar process using selective silicon deposition Method of manufacturing semiconductor device Method of fabricating a raised source/drain transistor Patent #: 5079180 InventorAssigneeApplicationNo. 596839 filed on 10/12/1990US Classes:438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)257/327, Short channel insulated gate field effect transistor257/E21.295, Deposition of layer comprising metal, e.g., metal, alloys, metal compounds (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E29.155, Multiple silicon layers257/E29.156, Including silicide layer contacting silicon layer (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/305Plural doping stepsExaminersPrimary: Wilczewski, MaryAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/336AbstractAn improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.Other References
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