Arrangement for testing digital circuit devices having tri-state outputs
Patent 5166937 Issued on November 24, 1992. Estimated Expiration Date: 
December 26, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 26, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.InventorAssigneeApplicationNo. 633847 filed on 12/26/1990US Classes:714/733, Built-in testing circuit (BILBO)714/724Digital logic testingExaminersPrimary: Canney, Vincent P.International ClassG01R 031/28AbstractAn arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group. | |
