Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
Process for fabricating semiconductor device
Process of fabricating three-dimensional semiconductor device
Via metallization using metal fillets
Method of selectively making contact structures both with barrier metal and without barrier metal in a single process flow
Semiconductor device and manufacturing method thereof
Method for simultaneously forming an interconnection level and via studs
Unframed via interconnection with dielectric etch stop
Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
Multilevel integrated circuits employing fused oxide layers
ApplicationNo. 638885 filed on 01/07/1991
US Classes:216/18, Filling or coating of groove or through hole with a conductor to form an electrical interconnection257/E23.145, Via connections in multilevel interconnection structure (EPO)438/628, Having adhesion promoting layer438/644Having adhesion promoting layer
ExaminersPrimary: Hearn, Brian E.
Assistant: Nguyen, Tan T.
International ClassH01L 021/44
AbstractA method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.