Patent 5159570 Issued on October 27, 1992. Estimated Expiration Date: May 7, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
365/185.03, Multiple values (e.g., analog)257/315, With floating gate electrode257/321, With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling257/E21.209, Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)257/E21.682, With source and drain on same level and without cell select transistor (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.129, Gate electrodes for transistors with floating gate (EPO)257/E29.306, Hot carrier injection from channel (EPO)257/E29.308, Programmable with more than two possible different levels (EPO)365/182, Insulated gate devices365/185.26Floating electrode (e.g., source, control gate, drain)
An EEPROM memory cell having sidewall floating gates (28, 28a, 28b) is disclosed. Sidewall floating gates (28, 28a, 28b) are formed on sidewalls (30, 32) of a central block (22). Spaced apart bit lines (36, 36a, 36b) are formed to serve as memory cell sources and drains. Sidewall floating gates (28a, 28b) are capable of being programmed independently of one another. When control gate (18) is actuated and either bit line (36a) or bit line (36b) is used to read the device, four separate memory states may be identified depending on whether either, neither or both of the sidewall floating gates (28a, 28b) have been programmed.