Fabricating an electrically-erasable, electrically-programmable read-only memory having a tunnel window insulator and thick oxide isolation between wordlines
January 31, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMOS double polysilicon read-only memory and cell Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same High density electrically programmable ROM High density, electrically erasable, floating gate memory cell High coupling ratio electrically programmable ROM Electrically erasable programmable read-only memory Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like Nonvolatile MOS memory cell with tunneling element Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell Semiconductor device InventorsAssigneeApplicationNo. 648087 filed on 01/31/1991US Classes:438/263, Tunneling insulator257/E27.103, Electrically programmable ROM (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)438/298, Doping region beneath recessed oxide (e.g., to form chanstop, etc.)438/981UTILIZING VARYING DIELECTRIC THICKNESSExaminersPrimary: Hearn, Brian E.Assistant: Chaudhari, C. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 021/76 AbstractAn electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized. | |
