Output circuit for a semiconductor memory device
Four-state I/O control circuit
Intermediate potential setting circuit
CMOS output circuit with intermediate potential setting means Patent #: 4988888
ApplicationNo. 743061 filed on 08/09/1991
US Classes:326/86, Bus driving326/17, ACCELERATING SWITCHING326/58, Complementary FET`s326/121CMOS
ExaminersPrimary: Westin, Edward P.
Assistant: Driscoll, Benjamin D.
Attorney, Agent or Firm
International ClassH03K 019/017.5
Foreign Application Priority Data1990-08-09 JP
AbstractAn output buffer unit comprises a controlling circuit responsive to an input data signal for producing a first controlling signal and a driving circuit implemented by a series combination of a p-channel type field effect transistor and an n-channel type field effect transistor complementarily shifted between on and off states for producing an output data signal, and a gating circuit is provided in association with the driving circuit so as to transfer a second controlling signal produced from the previous output data signal stored in a latching circuit to the field effect transistor for preliminarily changing the voltage level of an output data signal and, thereafter, to transfer the first controlling signal to the field effect transistor for finally determining the voltage level of the next output data signal so that the voltage level at the output node of the driving circuit quickly crosses over a discriminating level.