U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method for fabricating a multichip semiconductor device having two interdigitated leadframes

Patent 5147815 Issued on September 15, 1992. Estimated Expiration Date: Icon_subject March 1, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3808673

Integrated circuit package
Patent #: 4437235
Issued on: 03/20/1984
Inventor: McIver

Stacked interdigitated lead frame assembly
Patent #: 4496965
Issued on: 01/29/1985
Inventor: Orcutt ,   et al.

Plastic pin grid array chip carrier
Patent #: 4677526
Issued on: 06/30/1987
Inventor: Muehling

Method of assembling an optocoupler
Patent #: 4755474
Issued on: 07/05/1988
Inventor: Moyer

Packaging system for multiple semiconductor devices
Patent #: 4763188
Issued on: 08/09/1988
Inventor: Johnson

Peripheral/area wire bonding technique
Patent #: 4796078
Issued on: 01/03/1989
Inventor: Phelps, Jr. ,   et al.

Electronic component package using multi-level lead frames Patent #: 4801765
Issued on: 01/31/1989
Inventor: Moyer ,   et al.

Inventor

Assignee

Application

No. 663223 filed on 03/01/1991

US Classes:

29/827, Beam lead frame or beam lead device257/666, LEAD FRAME257/E23.038, Insulative substrate being used as die pad, e.g., ceramic, plastic (EPO)257/E23.042, Plurality of lead frames mounted in one device (EPO)257/E23.052, Assembly of semiconductor devices on lead frame (EPO)257/E23.128, Encapsulation having cavity (EPO)438/107, Assembly of plural semiconductive substrates each possessing electrical device438/123, Lead frame438/124And encapsulating

Examiners

Primary: Kunemund, Robert
Assistant: Graybill, David E.

Attorney, Agent or Firm

Foreign Patent References

  • 0397320A EP. 11/13/1990
  • 0062350 JP 05/13/1981
  • 0062351 JP 05/13/1981
  • 1-303730 JP 12/13/1989
  • 1-304757 JP 12/13/1989

International Classes

H01L 021/56
H01L 021/58
H01L 021/60

Abstract

A packaged semiconductor device is disclosed having at least two electronic components encapsulated in a single body of standard size and pin-out configuration. In accordance with one embodiment of this invention, two leadframes, having electronic components electrically coupled thereto, are positioned such that the electronic components are in a stacked relationship and the outer portions of the two sets of leads within each leadframe are interdigitated. The configuration enables all components to be accessed independently and minimizes the footprint of the device while maintaining a standard package outline.

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