Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof
Patent 5146583 Issued on September 8, 1992. Estimated Expiration Date: 
July 24, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 24, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesLogic Synthesizer In-circuit testing system Circuit translator Method of detecting constants and removing redundant connections in a logic network Multiple-precision Booth's recode multiplier Patent #: 4817029 InventorsAssigneeApplicationNo. 734113 filed on 07/24/1991US Classes:716/3, Translation (e.g., conversion, equivalence)706/921, Layout (e.g., circuit, construction)716/4Testing or evaluatingExaminersPrimary: Lee, Thomas C.Assistant: Mohamed, Ayni Attorney, Agent or FirmInternational ClassG06F 015/20Foreign Application Priority Data1987-09-25 JPAbstractAn apparatus and method for translating a function description of a circuit presented in hardware description language includes parsing the function description of the circuit to generate a parse tree. The structure of the parse tree is deformed to optimize the test level redundancy of the function description to thereby generate a deformed parse tree. The deformed parse tree is then translated into function blocks representing a hardware configuration of the circuit set forth by the function description. | |
