Managing high speed slow access channel to slow speed cyclic system data transfer
August 31, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInformation-signal recording apparatus employing record volume oriented identification signals Peripheral storage system having multiple data transfer rates Priority control apparatus for a bus in a bus control system having input/output devices Peripheral subsystem having read/write cache with record access Sequentially processing data in a cached data storage system Cache address comparator with sram having burst addressing control Arbitral dynamic cache using processor storage Sequentially processing data in a cached data storage system Patent #: 4956803 InventorsApplicationNo. 575748 filed on 08/31/1990US Classes:711/113CachingExaminersPrimary: Bowler, Alyssa H.Attorney, Agent or FirmInternational ClassesG06F 013/00G06F 013/12 AbstractA cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever reading a copy of the track contents stored in cache or the DASD reaches either an index mark, a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor data transfer operations are enabled.Field of SearchHaving particular data buffer or latch | |
