Stacked capacitor SRAM cell
Patent 5145799 Issued on September 8, 1992. Estimated Expiration Date: 
January 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesStatic memory having load polysilicon resistors formed over driver FET drains Static ram cell with trench pull-down transistors and buried-layer ground plate Semiconductor device sram to prevent out-diffusion CMOS device with both p+ and n+ gates Semiconductor device Multiple layer static random access memory device Patent #: 5001539 InventorAssigneeApplicationNo. 647579 filed on 01/30/1991US Classes:438/153, Complementary field effect transistors257/E21.008, Of capacitor (EPO)257/E21.661, Static random access memory structures (SRAM) (EPO)438/210Including passive device (e.g., resistor, capacitor, etc.)ExaminersPrimary: Chaudhuri, OlikAssistant: Trinh, Loc Q. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 021/265H01L 021/70 AbstractThis is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.Other References
| |
