Intercomputer communication control apparatus and method
October 7, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesModular terminal system using a common bus Interprocessor communication system Multiprocessor system Communication multiplexer having dual microprocessors Data processing system employing broadcast packet switching Multi-processor system with communication controller using poll flags for non-contentious slot reservation Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors Multiprocessor system comprising a plurality of data processors which are interconnected by a communication network Apparatus for transferring blocks of information from one node to a second node in a computer network Computer network system for multiple processing elements InventorsApplicationNo. 771889 filed on 10/07/1991US Classes:709/215, Partitioned shared memory710/260INTERRUPT PROCESSINGExaminersPrimary: Shaw, Gareth D.Assistant: Loomis, John C. Attorney, Agent or FirmInternational ClassG06F 013/14AbstractInterprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interrupt signal represented by the data. The stages of the register are connected to the associated interrupt input of the other processor.Other References
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