Methods and apparatus for caching interlock variables in an integrated cache memory
August 4, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3761883 Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands Cache synonym detection and handling means Cache memory architecture with decoding Three level memory hierarchy using write and share flags Multilevel cache system with graceful degradation capability Cache/disk file status indicator with data protection feature Cache locking controls in a multiprocessor Communicating random access memory Cache coherence mechanism based on locking InventorAssigneeApplicationNo. 146020 filed on 01/20/1988US Classes:711/139, No-cache flags711/128, Associative711/142Write-throughExaminersPrimary: Kriess, Kevin A.Attorney, Agent or FirmInternational ClassesG06F 015/16G06F 013/00 AbstractMethods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).Other References
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