Remote data link controller having multiple data link handling capabilities
Digital multi-customer data interface
Apparatus for interfacing between at least one channel and at least one bus
Digital communication network architecture for providing universal information services
Asynchronous packet manage
Packet bus interface
High speed digital signal framer-demultiplexer
Apparatus for reconstructing and multiplexing frames of various origins made up of a variable number of packets of fixed length
System and method for bridging local area networks using concurrent broadband channels
Buffer queue write pointer control circuit notably for self-channelling packet time-division switching system
ApplicationNo. 551700 filed on 07/11/1990
US Classes:370/399, Employing logical addressing for routing (e.g., VP or VC)370/419, Input or output circuit, per se (i.e., line interface)370/474Assembly or disassembly of messages having address headers
ExaminersPrimary: Olms, Douglas W.
Assistant: Samuel, T.
Attorney, Agent or Firm
International ClassH04J 003/24
AbstractA link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.