Local tristate control circuit
Patent 5136185 Issued on August 4, 1992. Estimated Expiration Date: 
September 20, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 20, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData output circuit with means for preventing more than half the output lines from transitioning simultaneously Configurable logic gate array Programmable logic array having an improved testing arrangement Method and circuitry for testing a programmable logic device Patent #: 5023485 InventorsApplicationNo. 763083 filed on 09/20/1991US Classes:326/16, WITH TEST FACILITATING FEATURE326/31, Signal level or switching threshold stabilization326/56, TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE)326/82Current driving (e.g., fan in/out, off chip driving, etc.)ExaminersPrimary: Westin, Edward P.Assistant: Sanders, Andrew International ClassesH03K 017/16H03K 019/173 AbstractThis invention improves and simplifies prior art systems for automatic test generation methodologies. In this invention, combinational logic is used to prevent opposing tristate bus drivers from simultaneously providing a logic signal on a common bus during testing of an integrated circuit. The combinational logic also ensures that at most one tristate buffer is enabled at all times during testing to ensure the common bus is at either a full logical 1, logical 0, or non-driven state. By preventing opposing drive signals being applied to the common bus and thus ensuring the bus is at a full logical 1 or logical 0 state when driven, automatic test generation programs can accurately generate test vectors for the integrated circuit. | |
