Method of making random access memory device having memory cells each implemented by a stacked storage capacitor and a transfer transistor with lightly-doped drain structure
Patent 5135881 Issued on August 4, 1992. Estimated Expiration Date: 
September 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for fabricating semiconductor memory device Patent #: 4977099 InventorAssigneeApplicationNo. 766258 filed on 09/27/1991US Classes:438/241, And additional field effect transistor (e.g., sense or access transistor, etc.)257/E21.648, Capacitor stacked over transfer transis tor (EPO)257/E21.654, Characterized by type of transistor; manufacturing of transistor (EPO)257/E27.086, Storage electrode stacked over the transistor438/253, Stacked capacitor438/305, Plural doping steps438/396, Stacked capacitor438/586Combined with formation of ohmic contact to semiconductor regionExaminersPrimary: Thomas, TomAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/70Foreign Application Priority Data1990-09-27 JPAbstractA random access memory device comprises a plurality of memory cells each having a transfer field effect transistor and a stacked type storage capacitor, a first inter-level insulating film provided between the transfer field effect transistor and the stacked type storage capacitor, and a peripheral circuit having a plurality of component transistors, and each of the component transistors has source and drain regions of an LDD structure, wherein the LDD structure is formed by using side walls made from an insulating film used for the first inter-level insulating film after the formation of the stacked type storage capacitor so that the source region of the transfer field effect transistor is not damaged by bombardment in an anisotropical etching for forming the side walls. | |
