High speed digital computing system
November 13, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3519810 3535502 3700875 Binary adder Integrated digital multiplier circuit using current mode logic High speed multiplier using carry-save/propagate pipeline with sparse carries One-bit full adder circuit Digital arithmetic unit having shortened processing time and a simplified structure Data processing system with an arithmetic logic unit having improved carry look ahead CMOS full adder circuit InventorsApplicationNo. 434612 filed on 11/13/1989US Classes:708/701, Bipolar junction transistor only or combined with Field-Effect Transistor708/708Carry-save addersExaminersPrimary: LaRoche, Eugene R.Assistant: Lee, Benny Attorney, Agent or FirmForeign Patent References
International ClassG06F 007/50AbstractA digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.Other References
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