U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor memory device having flip-flop circuits

Patent 5132771 Issued on July 21, 1992. Estimated Expiration Date: Icon_subject April 4, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Semiconductor memory device having stacked polycrystalline silicon layers
Patent #: 4481524
Issued on: 11/06/1984
Inventor: Tsujide

Semiconductor memory device
Patent #: 4535426
Issued on: 08/13/1985
Inventor: Ariizumi ,   et al.

Semiconductor integrated circuit
Patent #: 4609835
Issued on: 09/02/1986
Inventor: Sakai ,   et al.

Memory cell for SRAM with a dielectric layer over a gate electrode to provide a parallel resistive and capacitive element Patent #: 4797725
Issued on: 01/10/1989
Inventor: Hashimoto

Inventors

Assignee

Application

No. 503928 filed on 04/04/1990

US Classes:

257/524, Full dielectric isolation with polycrystalline semiconductor substrate257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/401, With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)257/544, With pn junction isolation257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E27.099, Load element being a MOSFET transistor (EPO)365/154, Flip-flop (electrical)365/156Complementary

Examiners

Primary: Hille, Rolf
Assistant: Limanek, Robert P.

Attorney, Agent or Firm

Foreign Patent References

  • 62-154287 JP. 07/13/1987

International Classes

H01L 029/04
H01L 027/02
H01L 029/10
H01L 029/06

Foreign Application Priority Data

1985-12-27 JP

Abstract

A semiconductor static random access memory having a high ଱-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

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