Patent ReferencesSemiconductor memory device having stacked polycrystalline silicon layers Semiconductor memory device Semiconductor integrated circuit Memory cell for SRAM with a dielectric layer over a gate electrode to provide a parallel resistive and capacitive element Patent #: 4797725 Inventors
AssigneeApplicationNo. 503928 filed on 04/04/1990US Classes:257/524, Full dielectric isolation with polycrystalline semiconductor substrate257/390, Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))257/401, With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET)257/544, With pn junction isolation257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E27.099, Load element being a MOSFET transistor (EPO)365/154, Flip-flop (electrical)365/156ComplementaryExaminersPrimary: Hille, RolfAssistant: Limanek, Robert P. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/04H01L 027/02 H01L 029/10 H01L 029/06 Foreign Application Priority Data1985-12-27 JPAbstractA semiconductor static random access memory having a high -ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another. | |