Method of producing a bipolar CMOS device
Patent 5132234 Issued on July 21, 1992. Estimated Expiration Date: 
July 9, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 9, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-aligned NPN bipolar transistor built in a double polysilicon CMOS technology Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts BiCMOS process and process for forming bipolar transistors on wafers also containing FETs Method of manufacturing a semiconductor device utilizing a single polycrystalline layer for all electrodes Method for forming emitters in a BiCMOS process Patent #: 5047357 InventorsApplicationNo. 727532 filed on 07/09/1991US Classes:438/203, Complementary bipolar transistors257/E21.173, Deposition of Schottky electrode (EPO)257/E21.612, Complementary vertical transistors (EPO)257/E21.696, Bipolar and MOS technologies (EPO)438/326Including additional electrical deviceExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmInternational ClassH01L 021/265Foreign Application Priority Data1991-02-25 KRAbstractA method of producing a bipolar CMOS device for providing a unipolar CMOS transistor with a polysilicon gate and a self-aligned NPN and VPNP transistor on a same chip, so that a high performance analog and digital BiCMOS device can be realized. | |
