System having a host independent input/output processor for controlling data transfer between a memory and a plurality of I/O controllers
July 14, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesControl apparatus for controlling data flow between a control processing unit and peripheral devices Data processor input/output controller Data processor input/output controller Multiprocessor mechanism for handling channel interrupts Data processing system including a separate input/output processor with micro-interrupt request apparatus Communication line status scan technique for a communications processing system Apparatus and method for extending a parallel channel to a serial I/O device Lockout operation among asynchronous accessers of a shared computer system resource Input/output system and method for digital computers Bus master capable of relinquishing bus on request and retrying bus cycle InventorsAssigneeApplicationNo. 327845 filed on 03/23/1989US Classes:710/22Direct Memory Accessing (DMA)ExaminersPrimary: Lee, Thomas C.Assistant: Lim, Krisna Attorney, Agent or FirmForeign Patent References
International ClassesG06F 013/12G06F 013/10 AbstractAn input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon. The I/O processor and I/O controllers may be interconnected with a local external memory via a local bus which is selectively coupled with a system bus interconnecting the main processor unit and main external memory.Other References
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