U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Operational track-and-hold amplifier

Patent 5130572 Issued on July 14, 1992. Estimated Expiration Date: Icon_subject December 26, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3838346

Differential sample-and-hold circuit
Patent #: 4370572
Issued on: 01/25/1983
Inventor: Cosand ,   et al.

Track-and-hold amplifier
Patent #: 4779012
Issued on: 10/18/1988
Inventor: Moscovici

Sample-and-hold circuit
Patent #: 4806790
Issued on: 02/21/1989
Inventor: Sone

Sampling and holding circuit for signal having low sampling residual component, especially for the dual sampling of a correlated signal given by a charge-transfer device
Patent #: 4845382
Issued on: 07/04/1989
Inventor: Eouzan ,   et al.

Low distortion sample and hold circuit Patent #: 5015877
Issued on: 05/14/1991
Inventor: King

Inventors

Assignee

Application

No. 633078 filed on 12/26/1990

US Classes:

327/96With differential amplifier

Examiners

Primary: Mullins, James B.

Attorney, Agent or Firm

International Class

H03K 005/159

Abstract

A track-and-hold circuit that consists of an operational amplifer wherein the same capacitors are used for phase compensation and as differential holding capacitors. The circuit is switched from track to hold by turning off the input stage by reverse biasing base-emitter junctions through current steering in combination with resistor clamping. Low impedance during the hold mode is maintained because one half of the differential compensation path is connected to the output. Feed-through is eliminated by cascoding the first stage and turning off the cascode devices through current steering with resistor clamping during the holding mode. The holding capacitors' droop due to bias currents is minimized by current cancellation of the second stage.

Other References

  • Delarue et al., "Control Circuit for Sample-and-Hold Devices", IBM Technical Disclosure Bulletin, vol. 19, No. 11 Apr. 1977, pp. 4211, 421
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