Low-latency two's complement bit-serial multiplier
Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals
Bit-sliced digit-serial multiplier
Serial-parallel multipliers using serial as well as parallel addition of partial products
Correction of systematic error in an oversampled analog-to-digital converter
Subsampling time-domain digital filter using sparsely clocked output latch Patent #: 4982353
AbstractA decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which waves decrements while the other increments, or vice versa. A digital multiplier is connected for receiving the time interleaved kernels and a stream of bits supplied at a rate that is one-quarter of which the filter clock pulses regularly recur. The multiplier's output is connected to the addend input of a parallel-bit adder. The adder's output is connected to a cascade connection of first, second, third and fourth clocked latches. The output signal of the fourth latch is supplied to the adder's augend input except during the first four clock pulse durations after the kernel values reach maxima. The output signal of the third latch is supplied to the adder's augend input during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the adder's augend input during the first and third clock pulse durations after the kernel values reach maxima. The filter's first and second output signals are extracted from the outputs of the second and fourth latches. This filter can be used on a single-channel basis. Alternatively, this filter is used on a dual-channel basis with a two-input multiplexer supplying the stream of bits to one of the multiplier's inputs. Also, plural of these filters can be joined to provide multiple-channel decimation filtering.