System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees
February 27, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMessage routing in a computer network Interconnection of broadcast networks Path oriented routing system and method for packet switching networks Method and apparatus for routing packets in a multinode computer interconnect network Methods and apparatus for efficient resource allocation Terminal for communication with a remote data processing system Process for determination of the last intermediate node in a network of numerous interconnected nodes Multiprocessor system comprising a plurality of data processors which are interconnected by a communication network Mesh-based switching network Dataflow processing element, multiprocessor, and processes InventorsApplicationNo. 488445 filed on 02/27/1990US Classes:709/245, COMPUTER-TO-COMPUTER DATA ADDRESSING370/406, Plurality of rings or loops to form a mesh network714/4Of networkExaminersPrimary: Lee, Thomas C.Assistant: Coleman, Eric Attorney, Agent or FirmInternational ClassG06F 013/00AbstractA network of interconnected processors is formed from a vertex symmetric graph selected from graphs Γd (k) with degree d, diameter k, and (d+1)!/(d-k+1)! processors for each dࣙk and Γd (k,-1) with degree 3-1, diameter k+1, and (d+1)!/(d-k+1)! processors for each dࣙkࣙ4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network Γd (k,-1) is provided, no processor has a channel connected to form an edge in a direction δ1. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations.Other References
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