Manufacturing method for semiconductor device
Patent 5120666 Issued on June 9, 1992. Estimated Expiration Date: 
May 2, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 2, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of fabricating silicon-on-insulator transistors with a shared element Process for manufacturing semiconductor devices containing microbridges Method of bonding semiconductor wafers Submerged wall isolation of silicon islands Patent #: 4888300 InventorAssigneeApplicationNo. 523679 filed on 05/02/1990US Classes:438/164, Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E29.137, Characterized by configuration of gate stack of thin film FETs (EPO)257/E29.275, With multiple gates (EPO)257/E29.281, For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO)257/E29.299, Characterized by property or structure of channel or contact thereto (EPO)438/157, Plural gate electrodes (e.g., dual gate, etc.)438/589Recessed into semiconductor substrateExaminersPrimary: Chaudhuri, OlikAssistant: Dang, Trung Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/265Foreign Application Priority Data1989-05-16 JPAbstractIn the manufacture of MISFETs using an Si layer island having an SOI structure, the present invention provides an Si layer over an SiO2 insulation layer, having a groove passing underneath the Si layer gate region and being formed on the surface of the SiO2 insulation layer by side etching conducted from both sides of the Si layer gate region, so as to form the source and drain. Next, after the SiO2 insulation layer is formed on the exposed surface of the Si layer gate electrode, a doped polysilicon region is formed through the SiO2 insulation film in such a manner that the groove and the area surrounding the Si layer gate region are filled, thereby forming the gate electrode. Thereafter, the MISFET is completed according to ordinary FET manufacturing methods. | |
