Three-dimensional contactless non-volatile memory cell
February 22, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesTriple layer polysilicon cell Floating gate storage device and method of fabrication Electrically programmable and electrically erasable MOS memory cell Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same Electrically erasable read only memory Process for fabricating a high density electrically programmable memory array Electrically programmable floating gate semiconductor memory device Virtual ground memory Single transistor electrically programmable memory device and method Method of making a non-volatile memory having dielectric filled trenches InventorApplicationNo. 483466 filed on 02/22/1990US Classes:365/185.29, Erase257/309, With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes)257/322, With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)257/E27.103, Electrically programmable ROM (EPO)257/E29.135, Characterized by length or sectional shape (EPO)257/E29.306Hot carrier injection from channel (EPO)ExaminersPrimary: Mintel, WilliamAssistant: Potter, Roy Attorney, Agent or FirmForeign Patent References
International ClassesH01L 029/68H01L 029/78 H01L 029/06 H01L 027/10 AbstractA three-dimensional contactless non-volatile memory cell is described. The memory cell comprises a substrate, source/drain regions that function as buried bit-lines and define a channel therebetween, a floating gate disposed above and insulated from the channel, and a control gate disposed above and insulated from the floating gate. The floating gate is formed to an adequate thickness so as to allow capacitive coupling to the control gate along the vertical regions of the floating gate. Thus, a reduction in minimum cell size can be achieved by decreasing the lateral dimensions of the cell without compromising the total capacitive coupling area. Subsequently, a substantial reduction in the total array area and a corresponding increase in device density can be realized. Further features of the invention include elimination of thick oxide regions in the array and improved gate oxide quality. | |
