All digital phase locked loop
December 24, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3238459 3839599 Digital clock recovery circuit Digital frequency and phase lock loop Arrangement for synchronizing the phase of a local clock signal with an input signal Method and means of clock recovery in a received stream of digital data Clock extraction circuit using an oscillator and phase-locked programmable divider Frequency synthesizer and digital phase lock loop PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction Phase-locked clock InventorsAssigneeApplicationNo. 633708 filed on 12/24/1990US Classes:375/373, Phase locking375/376Phase locked loopExaminersPrimary: Safourek, Benedict V.Assistant: Tse, Young T. Attorney, Agent or FirmInternational ClassH03D 003/24AbstractAn all-digital phase-locked loop (PLL) for synchronizing an output clock signal with a reference clock signal. The PLL has a multiple-tap, digital delay chain in its forward path for delaying the output clock signal, which delay chain is controlled by a digital number stored by a counter in its feedback path. A phase detector in the feedback path provides LEAD and LAG signals, the status of which indicates whether the output clock signal leads or lags the reference signal. In response to the LEAD and LAG signals, a digital sequencer in the feedback path generates the digital number and stores it in the counter. The digital sequencer changes the digital number until the state of the LEAD and LAG signals reverses, and then returns the counter back to its state prior to LEAD and LAG reversal, for synchronism. The digital sequencer also causes a phase reversal of the output signal where the number of delay taps needed for synchronism is large. As a result of the all-digital circuitry, use of unstable prior art voltage-controlled oscillators is obviated.Field of SearchAFC with logic elements | |
