Methods of making composite conductive structures in integrated circuits
Integrated circuit structure having intermediate metal silicide layer and method of making same
Method of making a planar structure containing MOS and bipolar transistors
Plugged poly silicon resistor load for static random access memory cells
Multiple step formation of conductive material layers
High speed double polycide bipolar/CMOS integrated circuit process Patent #: 4902640
ApplicationNo. 647709 filed on 01/28/1991
US Classes:438/384, Deposited thin film resistor257/E21.193, On single crystalline silicon (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)257/E21.575, Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO)257/E21.587, By deposition over sacrificial masking layer, e.g., lift-off (EPO)257/E21.696, Bipolar and MOS technologies (EPO)257/E29.114, Emitter or collector electrodes for bipolar transistors (EPO)257/E29.122, Characterized by relative position of source or drain electrode and gate electrode (EPO)438/210, Including passive device (e.g., resistor, capacitor, etc.)438/238, Including passive device (e.g., resistor, capacitor, etc.)438/385Altering resistivity of conductor
ExaminersPrimary: Quach, T. N.
Attorney, Agent or Firm
Foreign Patent References
International ClassesH01L 021/335
AbstractA process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.