Stacked bit-line architecture for high density cross-point memory cell array
April 20, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMOSFET Memory chip with single decoder and bi-level interconnect lines Flip-flop detector array for minimum geometry semiconductor memory apparatus DRAM with interleaved folded bit lines FET Storage with partitioned bit lines Semiconductor memory device High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor Bit line structure of dynamic type semiconductor memory device Patent #: 4922453 InventorsApplicationNo. 513315 filed on 04/20/1990US Classes:365/63, INTERCONNECTION ARRANGEMENTS257/302, Vertical transistor257/E27.096, Vertical transistor (EPO)365/72, Transistors or diodes365/149CapacitorsExaminersPrimary: Popek, Joseph A.Assistant: Whitfield, Michael A. Attorney, Agent or FirmInternational ClassesG11C 005/06G11C 011/24 AbstractA stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.Other References
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