U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

High-density, multi-level interconnects, flex circuits, and tape for tab

Patent 5106461 Issued on April 21, 1992. Estimated Expiration Date: Icon_subject December 21, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3868724

Multilayer flexible printed circuit tape
Patent #: 4064552
Issued on: 12/20/1977
Inventor: Angelucci ,   et al.

Bump circuits on tape utilizing chemical milling
Patent #: 4141782
Issued on: 02/27/1979
Inventor: Dugan ,   et al.

Apparatus for plating
Patent #: 4298446
Issued on: 11/03/1981
Inventor: Ando ,   et al.

Printed circuit lead carrier tape
Patent #: 4380042
Issued on: 04/12/1983
Inventor: Angelucci, Sr. ,   et al.

Process for making multilayer integrated circuit substrate
Patent #: 4386116
Issued on: 05/31/1983
Inventor: Nair ,   et al.

Apparatus and method for tape bonding and testing of integrated circuit chips
Patent #: 4411719
Issued on: 10/25/1983
Inventor: Lindberg

Method for forming conductive lines and vias
Patent #: 4430365
Issued on: 02/07/1984
Inventor: Schaible ,   et al.

Planarization of multi-level interconnected metallization system
Patent #: 4470874
Issued on: 09/11/1984
Inventor: Bartush ,   et al.

Area-bonding tape
Patent #: 4472876
Issued on: 09/25/1984
Inventor: Nelson

More ...

Inventors

Application

No. 632364 filed on 12/21/1990

US Classes:

205/125, Product is circuit board or printed circuit257/E23.173, Multilayer substrates (EPO)257/E23.174, Conductive vias through substrate with or without pins, e.g., buried coaxial conductors (EPO)257/E23.177, Flexible insulating substrates (EPO)438/616, By transcription from auxiliary substrate438/667, Conductive feedthrough or through-hole in substrate438/678, Electroless deposition of conductive layer438/977THINNING OR REMOVAL OF SUBSTRATE

Examiners

Primary: Hearn, Brian E.
Assistant: Dang, Trung

Attorney, Agent or Firm

International Class

C25D 005/00

Abstract

A multi-layer interconnect structure of alternating dielectric (e.g., polyimide) and metal (e.g., copper) is built on a substrate supporting a continuous layer of metal. This metal layer is used as an electrode for plating vias through all the dielectric layers. Once the desired number of layers are formed, the substrate is removed and the continuous metal layer is patterned. Solid metal vias having nearly vertical side walls can be stacked vertically, producing good electrical and thermal transfer paths and permitting small, closely-spaced conductors. Further, by mixing geometrical shapes of conductors, a variety of useful structures can be achieved, such as controlled impedance transmission lines and multiconductor TAB tape with interconnects on tape of different dimensions than TAB fingers.

Other References

  • Adams et al., "High Density Interconnect for Advanced VLSI Packaging", Suss Seminar Series, 1987, pp. 1-8
  • Barrett, "High Definition Electroplated Copper Conductors on Silicon and Ceramic", IMC Proceedings, May 25-27, 1988, pp. 461-467
  • Hatada et al., "New Film Carrier Assembly Technology: Transferred Bump TAB", IEEE, Sep. 1987, pp. 335-340
  • Heikkila, "Precision Plating: A Fundamental Approach", Economics Laboratory, Inc
  • Herrell, "I.C. Packaging Challenges", MCC Packaging/Interconnect Program, . . . , pp. 557-563
  • Hoffman, "TAB Implementation and Trends", Solid State Technology, Jun. 1988
  • Holzinger, "Advantages of a Floating Annular Ring in Three-Layer TAB Assembly", IEEE, Sep. 1987, pp. 332-334
  • Jardine, "Worldwide Tape Automated Bonding Marketplace", Electroni-Cast Corporation, . . . , pp. 1-3
  • Levinson et al., "High-Density Interconnects Wing Laser Lithography", G. E. Corp. Research and Development, pp. 1319-1327
  • Meyer, "Product Applications for Tape Automated Bonding", New Technology Concepts, pp. 1-5
  • Milosevic et al., "Polymide Enables High Lead Count TAB", Semiconductor International, Oct. 1988
  • Nelson, "Success of GaAs Semiconductos Hinges on Packaging", Electronic Packaging & Production, Jun. 1985
  • Neugebauer, "Multichip Module Designs for High Performance Application", G. E. Corp. Research & Development, pp. 401-413
  • Pedder, "Flip Chip Solder Bonding for Microelectronic Applications", Hybrid Circuits, Jan. 1, 1988, pp. 3-7
  • Poon et al., "High Density Multilevel Copper-Polyimide Interconnects," Microelectronics and Computer Tech. Corp., pp. 426-448
  • Speilberger et al., "Silicon-on-Silicon Packaging", IEEE, Jun. 1984, pp. 193-196
  • Jensen, "Polyamides as Interlayer Dielectrics for High Performance Interconnections of Integrated Circuits", Amer. Chem. Soc., 1987, 466-483
  • Kelly, "Tape Automated Bonding: The Answer to VLSI Packaging Problem?", Electronica, 12th International Congress, Munich, Nov. 86
  • Killam, "Development of Tape Automated Bonding for High Leadcount Integrated Circuits", National Semiconductor Corp., pp. 1-4
  • Levi, "Tape Pak (TM)-A Novel Approach to Packaging", Electronica, 12th International Congress, Munich, Nov. 86
  • Takiar, "TAB Technology-A Review", National Semiconductor Corp., pp. 1-3
  • Uehara, "Trends in TAB Technology", AEU, 1988, pp. 39-44
  • Vaz et al., "Effect of Bond Process Parameters on Aw/Aw Thermal Compression Tape Automated Bonding (TAB)", IEEE, 1987, pp. 22-23
  • Rogers Corporation-Simpson, "The Area Array Connector, A Pinless Connection Technique for Pad Grid Array Packages", 1987
  • Product Descriptions, Data Sheets and Bulletins
  • Overheads from a presentation by David J. Arthu
PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
 
Sign InRegister
Username  
Password   
forgot password?