Preimplanted N-channel SOI mesa
April 15, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing field-effect transistors by forming double insulative buried layers by ion-implantation Method of fabricating buried contacts Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state Process of making twin well VLSI CMOS Process for making junction field-effect transistors Method of making a thin film transistor with laser recrystallized source and drain Semiconductor device and method of making the same Semiconductor device that minimizes the leakage current associated with the parasitic edge transistors and a method of making the same High performance silicon-on-insulator transistor with body node to source node connection Making a silicon-on-insulator transistor with selectable body node to source node connection InventorApplicationNo. 684744 filed on 04/15/1991US Classes:438/164, Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E21.546, Using trench refilling with dielectric materials (EPO)257/E21.56, Dielectric isolation using EPIC technique, i.e., epitaxial passivated integrated circuit (EPO)257/E21.573, Air gaps (EPO)257/E21.703, Substrate is semiconductor body (EPO)257/E29.277Characterized by drain or source properties (EPO)ExaminersPrimary: Hearn, Brian E.Assistant: Picardat, Kevin M. International ClassH01L 021/265AbstractA silicon on insulator circuit having transistors formed in isolated mesas initially doped P-- has the mesas for N-channel transistors counterdoped to a N-- concentration, after which a field insulating layer is put down over an outer portion of the N-channel mesas and N-channel transistors with N+ sources and drains are formed, so that the N+ areas are adjacent the counterdoped N-- areas, thereby eliminating P-N junction found in prior art devices. | |
