U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Fault tolerant computer systems with fault isolation and repair

Patent 5099485 Issued on March 24, 1992. Estimated Expiration Date: Icon_subject May 25, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

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Bi-processor data handling system including automatic control of exchanges with external equipment and automatically activated maintenance operation
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Inventor: Censier ,   et al.

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System for manually or automatically transferring control between computers without power generation disturbance in an electric power plant or steam turbine operated by a multiple computer control system
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Input/output processing system utilizing locked processors
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Apparatus for facilitating a cooperation between an executive computer and a reserve computer
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Issued on: 07/04/1978
Inventor: Ossfeldt

Process control system with backup process controller
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Inventor: Keiles

Bus stab for panelboard assembly
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Inventor: Bishop ,   et al.

Parallel multiprocessing system for an industrial plant
Patent #: 4200226
Issued on: 04/29/1980
Inventor: Piras

Multiprocessor system
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Issued on: 10/14/1980
Inventor: Katzman ,   et al.

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Inventors

Assignee

Application

No. 357626 filed on 05/25/1989

US Classes:

714/11Concurrent, redundantly operating processors

Examiners

Primary: Beausoliel, Robert

Attorney, Agent or Firm

Foreign Patent References

  • WO81/00925 EP. 04/13/1981
  • 1200155 GB. 04/13/1970

International Classes

G06F 011/30
G06F 011/16

Abstract

A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.

Other References

  • Chester, "Fault-Tolerant Computers Mature," Systems & Software, pp. 117-129 (Mar., 1985)
  • Depledge, et al., "Fault-Tolerant Microcomputer Systems for Aircraft," IERE Conference Proceedings 36, 1977, Proc. Conf. on Computer Systems & Technology Engineering, pp. 205-220 (Mar., 1977)
  • Beck, et al., "Implementation Issues in Clock Synchronization," Mar. 15, 1986 Draft (origin unknown)
  • Datapro Research Corporation Feature Report (Dec. 1985), M07-100-318 to M07-100-323
  • IBM System/88, The Operating System Reference
  • Harrison, "S/88 Architecture and Design; S/88 Internals, Share 67" (8/12/86)
  • "System/88 Technical Overview" (date believed to be 2/86)
  • Tandem NonStop Computers, Datapro Research Corporation, Computers M11-822-101 to M11-822-119 (Oct., 1986)
  • Bartlett, "The Tandem Concept of Fault-Tolerance," (view 1985), M07-100-318 to M07-100-323
  • Bernstein, "Sequoia: A Fault-Tolerant Tightly-Coupled Computer for Transaction Processing," Technical Report TR-85-03, pp. 1-43 (May 2, 1985)
  • Sequoia Technical Overview (data unknown but believed to be Mar., 1985 by virtue of annotation at the bottom of last page of this material)
  • Sequoia Hardware Architecture (1984)
  • Bernstein, Sequoia, Wang Institute of Graduate Studies (date unknown)
  • "How Technology is Cutting Fault-Tolerance Costs," Electronics 55-58 (Jan. 13, 1986)
  • Katsuki, et al., "Pluribus-An Operational Fault-Tolerant Multiprocessor," Proceedings of the IEEE vol. 66, No. 10 (Oct., 1978)
  • Reynolds, "Architectures for Fault-Tolerant Spacecraft Computers," Proceedings of the IEEE, vol. 66, No. 10, pp. 1255-1268 (Oct., 1978)
  • Parallel 300 (1984)
  • Inselberg, "Multiprocessor Architecture Ensures Fault-Tolerant Transaction Processing," Many MicroSystems (Apr. 1983)
  • Anita Borg, "Targon/Nixdorf" (date unknown)
  • Losq, "A Highly Efficient Redundancy Scheme: Self-Purging Redundancy," IEEE Transactions on Computers, vol. C-25, No. 6 (Jun., 1986)
  • Su, et al., "A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures," IEEE Transactions on Computers, vol. C-29, No. 3, (Mar., 1980)
  • Takaoka, et al., "N-Fail-Safe Logical Systems," IEEE Transactions on Computers, vol. C-20, No. 5, pp. 536-54
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