Composite inverse T-gate metal oxide semiconductor device and method of fabrication
Patent 5097301 Issued on March 17, 1992. Estimated Expiration Date: 
December 19, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 19, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDouble implanted LDD transistor self-aligned with gate Submicron lightly doped field effect transistors LDD transistor process having doping sensitive endpoint etching MOS transistors using selective polysilicon deposition Patent #: 4984042 InventorApplicationNo. 630155 filed on 12/19/1990US Classes:257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/412, Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)257/E29.128, With insulated gate (EPO)257/E29.269With overlap between lightly doped extension and gate electrode (EPO)ExaminersPrimary: Prenty, Mark V.Attorney, Agent or FirmInternational ClassesH01L 029/10H01L 029/06 H01L 029/04 H01L 027/01 AbstractA high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation. An inverse T-gate comprising a polysilicon upper member and a tungsten lower member is formed on a p type substrate. A gate insulating layer is formed between the composite gate and the p type substrate. A pair of n- source/drain regions are formed apart in the p type substrate in alignment with the sides of the polysilicon upper member for forming a lightly doped drain region. An oxide sidewall spacer is formed adjacent to each side of the polysilicon upper member on the tungsten lower gate member for forming a mask for a n+ source/drain implant. The n+ source/drain implant is made in the n- source/drain regions in alignment with the oxide sidewall spacers for providing a source and a drain for the transistor. The tungsten lower gate member improves the transistors performance and makes the transistor viable for VLSI manufacturing techniques. The performance of the device can be further improved by placing silicide on the source gate, and drain regions. The reliability of the device can be further improved by grading the doping of the drain an additional time.Other References
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