Self-aligned overlap MOSFET and method of fabrication
Patent 5091763 Issued on February 25, 1992. Estimated Expiration Date: 
December 19, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 19, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDevice and process with doubled capacitors Gate controllable lightly doped drain mosfet devices Patent #: 4868617 InventorApplicationNo. 630285 filed on 12/19/1990US Classes:257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/346, Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/900, MOSFET TYPE GATE SIDEWALL INSULATING SPACER257/915, WITH TITANIUM NITRIDE PORTION OR REGION257/E21.21, Comprising charge trapping insulator (EPO)257/E21.346, Using mask (EPO)257/E29.141, Resistive materials for field-effect devices (EPO)257/E29.269, With overlap between lightly doped extension and gate electrode (EPO)438/304, Conductive sidewall component438/596Portion of sidewall structure is conductiveExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmInternational ClassesH01L 029/06H01L 021/265 AbstractA high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.Other References
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