Method of fabricating MOS transistors using selective polysilicon deposition
August 17, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for the production of a MIS transistor with a raised substrate/gate dielectric interface end Process for elevated source/drain field effect structure Method of making an integrated circuit resistor Method for fabricating double implanted LDD transistor self-aligned with gate Selective deposition of amorphous and polycrystalline silicon Contact structure and method Method of constructing lightly doped drain (LDD) integrated circuit structure Patent #: 4975385 InventorsAssigneeApplicationNo. 569097 filed on 08/17/1990US Classes:438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E29.051, With insulated gate (EPO)257/E29.054, Doping structure being parallel to channel length (EPO)257/E29.269, With overlap between lightly doped extension and gate electrode (EPO)438/291, Using channel conductivity dopant of opposite type as that of source and drain438/305, Plural doping steps438/595Having sidewall structureExaminersPrimary: Chaudhuri, OlikAssistant: Wilczewski, M. Attorney, Agent or FirmInternational ClassesH01L 021/28H01L 021/336 AbstractIn forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.Other References
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