Digital phase aligner and method for its operation
December 7, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAutomatic data synchronizer Digital clock recovery circuit Digital phase correlator Vertical video centering control system Digital phase lock loop circuit Automatic signal delay adjustment apparatus Automatic signal delay adjustment method Automatic clock de-skewing apparatus Digital phase aligner Phase and frequency detector circuits InventorAssigneeApplicationNo. 447326 filed on 12/07/1989US Classes:375/373, Phase locking327/231, Phase shift by less than period of input331/1A, AFC with logic elements375/374With charge pump or up and down countersExaminersPrimary: Chin, StephenAttorney, Agent or FirmInternational ClassH03D 003/24Foreign Application Priority Data1989-10-23 CAAbstractIn methods and apparatus for aligning the phase of a local clock signal with the phase of a data signal, an incoming data signal is delayed to provide a delayed data signal and regenerated with a local clock signal to provide a regenerated data signal. A difference between the phase of the delayed data signal and the phase of the regenerated data signal is detected. The phase of the local clock signal is retarded by a predetermined fraction of a bit period if the regenerated data signal leads the delayed data signal and is advanced by the predetermined fraction of the bit period if the regenerated data signal lags the delayed data signal. The retiming, detecting, retarding and advancing steps are repeated continuously to obtain and maintain approximate alignment of the phase of the local clock signal with the phase of the delayed data signal. The methods and apparatus are useful in high speed packet switches.Other References
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