U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of fabricating a raised source/drain transistor

Patent 5079180 Issued on January 7, 1992. Estimated Expiration Date: Icon_subject August 16, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Self-aligned metal process for field effect transistor integrated circuits
Patent #: 4359816
Issued on: 11/23/1982
Inventor: Abbas ,   et al.

Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
Patent #: 4378627
Issued on: 04/05/1983
Inventor: Jambotkar

Method of fabricating a monolithic integrated circuit structure
Patent #: 4463491
Issued on: 08/07/1984
Inventor: Goldman ,   et al.

Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
Patent #: 4471522
Issued on: 09/18/1984
Inventor: Jambotkar

Production of cupric and manganous alkanoates
Patent #: 4485046
Issued on: 11/27/1984
Inventor: Fruchey

Method of making submicron FET structure
Patent #: 4546535
Issued on: 10/15/1985
Inventor: Shepard

Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions
Patent #: 4677736
Issued on: 07/07/1987
Inventor: Brown

Method of making a planar MOS device in polysilicon
Patent #: 4688314
Issued on: 08/25/1987
Inventor: Weinberg ,   et al.

Method of making a planar structure containing MOS and bipolar transistors
Patent #: 4707456
Issued on: 11/17/1987
Inventor: Thomas ,   et al.

Manufacturing MOS semiconductor device with planarized conductive layer
Patent #: 4713356
Issued on: 12/15/1987
Inventor: Hiruta

More ...

Inventors

Assignee

Application

No. 568305 filed on 08/16/1990

US Classes:

438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)438/305Plural doping steps

Examiners

Primary: Chaudhuri, Olik
Assistant: Wilczewski, M.

Attorney, Agent or Firm

Foreign Patent References

  • 0121580 JP 10/12/1978
  • 0196573 JP 12/12/1982
  • 0148367 JP 08/12/1984
  • 0082456 JP 04/12/1986
  • 0147774 JP 07/12/1987

International Class

H01L 021/336

Abstract

A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?