Quotables
"There is practically no chance communications space satellites will be used to provide better telephone, telegraph, television, or radio service inside the United States."
T. Craven, FCC Commissioner ; 1961
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
US Patent 5079180 - Method of fabricating a raised source/drain transistor
US Patent Issued on January 7, 1992
Estimated Patent Expiration Date:
August 16, 2010Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
August 16, 2010Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60). | InventorsAssigneeApplicationNo. 568305 filed on 08/16/1990US Classes:438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)438/305Plural doping stepsExaminersPrimary: Chaudhuri, OlikAssistant: Wilczewski, M. Attorney, Agent or FirmUS Patent References4359816, Self-aligned metal process for field effect transistor integrated circuitsIssued on: 11/23/1982 Inventor: Abbas , et al.4378627, Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Issued on: 04/05/1983 Inventor: Jambotkar4463491, Method of fabricating a monolithic integrated circuit structure Issued on: 08/07/1984 Inventor: Goldman , et al.4471522, Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes Issued on: 09/18/1984 Inventor: Jambotkar4485046, Production of cupric and manganous alkanoates Issued on: 11/27/1984 Inventor: Fruchey4546535, Method of making submicron FET structure Issued on: 10/15/1985 Inventor: Shepard4677736, Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions Issued on: 07/07/1987 Inventor: Brown4688314, Method of making a planar MOS device in polysilicon Issued on: 08/25/1987 Inventor: Weinberg , et al.4707456, Method of making a planar structure containing MOS and bipolar transistors Issued on: 11/17/1987 Inventor: Thomas , et al.4713356, Manufacturing MOS semiconductor device with planarized conductive layer Issued on: 12/15/1987 Inventor: Hiruta4735916, Method of fabricating bipolar transistors and insulated gate field effect transistors having doped polycrystalline silicon conductors Issued on: 04/05/1988 Inventor: Homma , et al.4745086, Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation Issued on: 05/17/1988 Inventor: Parrillo , et al.4764481, Grown side-wall silicided source/drain self-align CMOS fabrication process Issued on: 08/16/1988 Inventor: Alvi , et al.4778774, Process for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor Issued on: 10/18/1988 Inventor: Blossfeld4780429, Method of fabrication of MOS transistors having electrodes of metallic silicide Issued on: 10/25/1988 Inventor: Roche , et al.4788160, Process for formation of shallow silicided junctions Issued on: 11/29/1988 Inventor: Havemann , et al.4822754, Fabrication of FETs with source and drain contacts aligned with the gate electrode Issued on: 04/18/1989 Inventor: Lynch , et al.4826782, Method of fabricating aLDD field-effect transistor Issued on: 05/02/1989 Inventor: Sachitano , et al.4844776, Method for making folded extended window field effect transistor Issued on: 07/04/1989 Inventor: Lee , et al.4868137, Method of making insulated-gate field effect transistor Issued on: 09/19/1989 Inventor: Kubota4874713, Method of making asymmetrically optimized CMOS field effect transistors Issued on: 10/17/1989 Inventor: Gioia4888297, Process for making a contact structure including polysilicon and metal alloys Issued on: 12/19/1989 Inventor: Aboelfotoh, et al.4939154, Method of fabricating an insulated gate semiconductor device having a self-aligned gate Issued on: 07/03/1990 Inventor: Shimbo4945070, Method of making cmos with shallow source and drain junctions Issued on: 07/31/1990 Inventor: Hsu4948743, Method of manufacturing a semiconductor device Issued on: 08/14/1990 Inventor: Ozaki4948745, Process for elevated source/drain field effect structure Issued on: 08/14/1990 Inventor: Pfiester, et al.4965219Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits Issued on: 10/23/1990 Inventor: Cerofolini Foreign Patent References
International ClassH01L 021/336 |
