Self-aligned metal process for field effect transistor integrated circuits
Patent #: 4359816
Issued on: 11/23/1982
Inventor: Abbas , et al.
Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
Patent #: 4378627
Issued on: 04/05/1983
Inventor: Jambotkar
Method of fabricating a monolithic integrated circuit structure
Patent #: 4463491
Issued on: 08/07/1984
Inventor: Goldman , et al.
Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
Patent #: 4471522
Issued on: 09/18/1984
Inventor: Jambotkar
Production of cupric and manganous alkanoates
Patent #: 4485046
Issued on: 11/27/1984
Inventor: Fruchey
Method of making submicron FET structure
Patent #: 4546535
Issued on: 10/15/1985
Inventor: Shepard
Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions
Patent #: 4677736
Issued on: 07/07/1987
Inventor: Brown
Method of making a planar MOS device in polysilicon
Patent #: 4688314
Issued on: 08/25/1987
Inventor: Weinberg , et al.
Method of making a planar structure containing MOS and bipolar transistors
Patent #: 4707456
Issued on: 11/17/1987
Inventor: Thomas , et al.
Manufacturing MOS semiconductor device with planarized conductive layer
Patent #: 4713356
Issued on: 12/15/1987
Inventor: Hiruta
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Method of fabricating bipolar transistors and insulated gate field effect transistors having doped polycrystalline silicon conductors
Patent #: 4735916
Issued on: 04/05/1988
Inventor: Homma , et al.
Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation
Patent #: 4745086
Issued on: 05/17/1988
Inventor: Parrillo , et al.
Grown side-wall silicided source/drain self-align CMOS fabrication process
Patent #: 4764481
Issued on: 08/16/1988
Inventor: Alvi , et al.
Process for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor
Patent #: 4778774
Issued on: 10/18/1988
Inventor: Blossfeld
Method of fabrication of MOS transistors having electrodes of metallic silicide
Patent #: 4780429
Issued on: 10/25/1988
Inventor: Roche , et al.
Process for formation of shallow silicided junctions
Patent #: 4788160
Issued on: 11/29/1988
Inventor: Havemann , et al.
Fabrication of FETs with source and drain contacts aligned with the gate electrode
Patent #: 4822754
Issued on: 04/18/1989
Inventor: Lynch , et al.
Method of fabricating aLDD field-effect transistor
Patent #: 4826782
Issued on: 05/02/1989
Inventor: Sachitano , et al.
Method for making folded extended window field effect transistor
Patent #: 4844776
Issued on: 07/04/1989
Inventor: Lee , et al.
Method of making insulated-gate field effect transistor
Patent #: 4868137
Issued on: 09/19/1989
Inventor: Kubota
Method of making asymmetrically optimized CMOS field effect transistors
Patent #: 4874713
Issued on: 10/17/1989
Inventor: Gioia
Process for making a contact structure including polysilicon and metal alloys
Patent #: 4888297
Issued on: 12/19/1989
Inventor: Aboelfotoh, et al.
Method of fabricating an insulated gate semiconductor device having a self-aligned gate
Patent #: 4939154
Issued on: 07/03/1990
Inventor: Shimbo
Method of making cmos with shallow source and drain junctions
Patent #: 4945070
Issued on: 07/31/1990
Inventor: Hsu
Method of manufacturing a semiconductor device
Patent #: 4948743
Issued on: 08/14/1990
Inventor: Ozaki
Process for elevated source/drain field effect structure
Patent #: 4948745
Issued on: 08/14/1990
Inventor: Pfiester, et al.
Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits Patent #: 4965219
Issued on: 10/23/1990
Inventor: Cerofolini