U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method and apparatus for storing digital data in off-specification dynamic random access memory devices

Patent 5077737 Issued on December 31, 1991. Estimated Expiration Date: Icon_subject August 18, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3633175

Fault-tolerant cell addressable array
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Defect tolerant memory
Patent #: 4380066
Issued on: 04/12/1983
Inventor: Spencer ,   et al.

EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like
Patent #: 4393474
Issued on: 07/12/1983
Inventor: McElroy

Combined serializer encoder and decoder for data storage system
Patent #: 4398225
Issued on: 08/09/1983
Inventor: Cornaby ,   et al.

Multiple error detecting and correcting system employing Reed-Solomon codes
Patent #: 4413339
Issued on: 11/01/1983
Inventor: Riggle ,   et al.

System for updating error map of fault tolerant memory
Patent #: 4479214
Issued on: 10/23/1984
Inventor: Ryan

Self repairing bulk memory
Patent #: 4493075
Issued on: 01/08/1985
Inventor: Anderson ,   et al.

Systematic memory error detection and correction apparatus and method
Patent #: 4506362
Issued on: 03/19/1985
Inventor: Morley

Remap method and apparatus for a memory system which uses partially good memory devices
Patent #: 4527251
Issued on: 07/02/1985
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Inventors

Application

No. 395485 filed on 08/18/1989

US Classes:

714/6, Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)714/723Error mapping or logging

Examiners

Primary: Smith, Jerry
Assistant: Hua, Ly V.

Attorney, Agent or Firm

International Class

G06F 011/00

Abstract

A fault-tolerant memory system or "FTMS" is intended for use as mass data storage for a host computer system. The FTMS incorporates a dedicated microprocessor-controlled computer system which serializes blocks of user data as they are received from the host system, deserializes those blocks when they are returned to the host system, implements an error correction code system for the user data blocks, scrubs the data stored in the user memory, remaps data block storage locations within the user memory as initial storage locations therein acquire too may hard errors for error correction to be effected with the stored error correction data, and performs host computer interface operations. Data in the FTMS is not bit-addressable. Instead, serialization of the user data permits bytes to be stored sequentially within the user memory much as they would be stored on a hard disk, with bytes being aligned in the predominant direction of serial bit failure within the off-spec DRAM devices. Such a data storage method facilitates error correction capability.

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