Patent References 3633175 Fault-tolerant cell addressable array Defect tolerant memory EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like Combined serializer encoder and decoder for data storage system Multiple error detecting and correcting system employing Reed-Solomon codes System for updating error map of fault tolerant memory Self repairing bulk memory Systematic memory error detection and correction apparatus and method Remap method and apparatus for a memory system which uses partially good memory devices InventorsApplicationNo. 395485 filed on 08/18/1989US Classes:714/6, Redundant stored data accessed (e.g., duplicated data, error correction coded data, or other parity-type data)714/723Error mapping or loggingExaminersPrimary: Smith, JerryAssistant: Hua, Ly V. Attorney, Agent or FirmInternational ClassG06F 011/00AbstractA fault-tolerant memory system or "FTMS" is intended for use as mass data storage for a host computer system. The FTMS incorporates a dedicated microprocessor-controlled computer system which serializes blocks of user data as they are received from the host system, deserializes those blocks when they are returned to the host system, implements an error correction code system for the user data blocks, scrubs the data stored in the user memory, remaps data block storage locations within the user memory as initial storage locations therein acquire too may hard errors for error correction to be effected with the stored error correction data, and performs host computer interface operations. Data in the FTMS is not bit-addressable. Instead, serialization of the user data permits bytes to be stored sequentially within the user memory much as they would be stored on a hard disk, with bytes being aligned in the predominant direction of serial bit failure within the off-spec DRAM devices. Such a data storage method facilitates error correction capability. | |