Probabilistic inference gate
Patent 5077677 Issued on December 31, 1991. Estimated Expiration Date: 
June 12, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 12, 2009. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3259735 3757261 3803390 Probabilistic learning element Digital parallel computing circuit for computing p=xy+z in a shortened time Probabilistic learning element employing context drive searching Digital signal processing circuit Multi-level logic circuit Probabilistic learning element Apparatus and method for implementing dilation and erosion transformations in grayscale image processing InventorsAssigneeApplicationNo. 364475 filed on 06/12/1989US Classes:706/62, MISCELLANEOUS706/52, Reasoning under uncertainty (e.g., fuzzy logic)706/900, FUZZY LOGIC708/490Arithmetical operationExaminersPrimary: MacDonald, Allen R.Attorney, Agent or FirmInternational ClassG06F 015/18AbstractThe present system performs linear transformations on input probabilities and produces outputs which indicate the likelihood of one or more events. The transformation performed is a product of linear transforms such as Po =[Aj Pj +Bj ]⋅[Ak Pk +Bk ] where Pj and Pk are input probabilities, Po is an output event probability and Aj, Bj, Ak and Bk are transformation constants. The system includes a basic processing unit or computational unit which performs a probabilistic gate operation to convert two input probability signals into one output probability signal where the output probability is equal to the product of linear transformations of the input probabilities. By appropriate selection of transformation constants logical and probabilistic gates performing the functions of AND, NAND, OR, NOR, XOR, NOT, IMPLIES and NOT IMPLIES can be created. The basic unit can include three multipliers and two adders if a discrete component hardwired version is needed for speed or a single multiplier/adder, associated storage and multiplex circuits can be used to accomplish the functions of the hardwired version for economy. This basic unit can also be provided as a software implementation, can be implemented as a hardwired decision tree element implementation or implemented as a universal probabilistic processor and provided with a bus communication structure to create expert systems or neural networks suitable for specific tasks. The basic units can be combined to produce a virtual basic building block which has more virtual processors than physical processors to improve processor utilization. The building blocks can be combined into an array to produce either a high speed expert system or a high speed neural network.Other References
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