Patent ReferencesMethod for forming buried contact complementary MOS devices CMOS Device with silicided sources and drains and method Semiconductor device and method for manufacturing the same Device for semiconductor integrated circuits Self-aligned stacked CMOS Method of manufacturing a semiconductor device comprising resistors of high and low resistances Semiconductor on insulator edge doping process using an expanded mask Method for fabricating stacked CMOS transistors with a self-aligned silicide process Stacked complementary metal oxide semiconductor inverter Five transistor CMOS memory cell including diodes InventorsApplicationNo. 380175 filed on 07/13/1989US Classes:438/155, And additional electrical device on insulating substrate or layer257/E21.593, By forming silicide of refractory metal (EPO)257/E21.704, Substrate is nonsemiconductor body, e.g., insulating body (EPO)257/E23.016, For devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g., silicon on sapphire devices, i.e., SOS (EPO)438/154Complementary field effect transistorsExaminersPrimary: Hearn, Brian E.Assistant: Nguyen, Tan T. Attorney, Agent or FirmForeign Patent References
International ClassH01L 021/283AbstractA process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.Other References
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