Logic level shifting circuit with minimal delay
Patent 5059829 Issued on October 22, 1991. Estimated Expiration Date: 
September 4, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 4, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMemory device with improved common data line bias arrangement ECL-compatible input/output circuits in CMOS technology ECL to CMOS converter FET buffer amplifier Patent #: 4916338 InventorsAssigneeApplicationNo. 577178 filed on 09/04/1990US Classes:326/66, ECL to/from CMOS326/17, ACCELERATING SWITCHING330/253Having field effect transistorExaminersPrimary: Westin, Edward P.Assistant: Bertelson, David R. Attorney, Agent or FirmInternational ClassesH03K 019/092H03K 019/094 H03K 019/01 H03K 019/003 AbstractA circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time. | |
